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S75NS-N
S29NS-N: MirrorBitTM 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) S30MS-P: ORNANDTM Flash (NAND interface) Multiplexed Synchronous pSRAM
Data Sheet (Advance Information)
S75NS-N Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S75NS-N_00
Revision 01E
Issue Date May 3, 2006
Data
Sheet
(Advance
Information)
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
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S75NS-N
May 3, 2006 S75NS-N_00-01E
S75NS-N
S29NS-N: MirrorBitTM 1.8 Volt-only Simultaneous Read/ Write, Burst-mode Multiplexed Flash (NOR Interface) S30MS-P: ORNANDTM Flash (NAND interface) Multiplexed Synchronous pSRAM
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V Burst Speed: 66 MHz Package - MCP BGA: 0.5 mm ball pitch
- 11 x 13 x 1.4 mm, 112 ball
Operating Temperature
- Wireless, -25C to +85C
General Description
The S75NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: S29NS-N S30MS-P Mux pSRAM The products covered by this document are listed in the tables below.
pSRAM S29NS128 + S30MS512P S30MS01GP 32 Mb S75NS128NBF S75NS128NBG
Product Selector Guide
Device S75NS128NBF S75NS128NBG pSRAM Density 32 Mb 32 Mb pSRAM Type Multiplexed pSRAM Type 3 Multiplexed pSRAM Type 3
For detailed specifications, please refer to the individual data sheets:
Document S29NS-N S30MS-P 32 Mb Multiplexed pSRAM Type 3 Publication Identification Number S29NS-N_00 S30MS-P_00 muxpsram_04
Publication Number S75NS-N_00
Revision 01E
Issue Date May 3, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Advance
Information)
1.
Ordering Information
The ordering part number is formed by a valid combination of the following:
S75NS 128
N
B
G
J
W
JZ
0 Packing Type 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel Model Number Refer to the Valid Combinations table below Temperature Range W = Wireless (-25C to +85C) Package Type J = 1.4 mm height, 0.5mm ball size, Thin Fine-Pitch Ball Grid Array (FBGA) Lead (Pb)-free Package (LF35) ORNAND Data Density F = 512 Mb G = 01 Gb pSRAM Density B = 32 Mb C = 64 Mb Process Technology N = 110 nm MirrorBit Technology Flash Density 256 = 256 Mb 128 = 128 Mb Device Family S75NS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/ Write Burst Mode Multiplexed Flash Memory + pSRAM + ORNAND Data Storage
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Table 1.1 MCP Configurations and Valid Combinations
Base Ordering Part Number (Note 2) S75NS128NBF UJW S75NS128NBG JZ Package & Temperature Model Number JZ 0, 2, 3 pSRAM Type 3 66 MHz 66 MHz Packing Type pSRAM Type pSRAM Type 3 Flash Speed Options 66 MHz pSRAM Speed Options 66 MHz
Notes: 1. Type 0 is standard. Specify other options as required. 2. The package marking omits the leading S and packing type designator from the ordering part number. 3. Contact factory for availability of any of the OPNs listed because RAM type availability may vary over time.
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2.
Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions
Symbol AMAX - A16 ADQ15 - ADQ0 OE# WE# VSS F-RDY / R-WAIT Signal Type Input I/O Input Input Ground Output Address inputs Multiplexed Address/Data Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Ground Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY. Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. Flash 1.8 Volt-only single power supply Chip-enable input for pSRAM Control Register Enable (pSRAM) pSRAM Power Supply Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Command Latch Enable Address Latch Enable Chip Enable input for ORNAND Write Enable input Read Enable input Data Input/Output Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Ready/Busy output Power-On Read Enable Ground ORNAND 1.8 Volt-only single power supply. Do Not Use No Connect; not connected internally Description NS (NOR) X X X X X X pSRAM X X X X X X MS (ORNAND)
CLK
Input
X
X
AVD#
Input
X
X
F-RST#
Input
X
F-WP#
Input
X
F-ACC
Input
X
F-CE# VCC R-CE1# R-CRE R-VCC R-UB# R-LB# N-CLE N-ALE N-CE# N-WE# N-RE# N-IO0 - N-IO7 N-WP# N-RY/BY# N-PRE N-VSS N-VCC DNU NC
Input Power Input Input Power Input Input Input Input Input Input Input I/O Input Input Input Ground Power -- --
X X X X X X X X X X X X X X X X X X X
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3.
MCP Block Diagram
Figure 3.1 MCP Block Diagram
A21-A22 A15-A0 DQ15-DQ0 CLK RDY A21-A22 ADQ15-ADQ 0 CLK F-RDY/R-WAIT
F-RST# F-ACC F-WP# F-CE# OE# WE# AVD# VSS VSSQ
RST# ACC WP# CE# OE# WE# AVD# VSS VSSQ
Mux FLASH MEMORY
A16-A20 VCC VCCQ
A16-A20 VCC VCCQ
R-UB# R-LB# R-CE1#
UB# LB# CE# OE# WE# AVD# CRE VSS VSSQ
Mux Sync pSRAM MEMORY
A15-A0 DQ15-DQ0 CLK WAIT
A16-A20 VCC VCCQ
R-CRE
I/O0-I/O7
N-RY/BY#
N-IO0 - N-IO7
RB#
N-PRE N-CLE N-CE# N-ALE N-RE# N-WP# N-WE#
PRE CLE CE# ALE RE# WP# WE#
x8 ORNAND Flash Memory
VSS
N-VSS
VCC
N-VCC
4. Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71NS-N.
4.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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Information)
4.2
Connection Diagrams
1 A NC B NC C NC D NC E DNU F N-CE# G N-VCC N-VCC H N-VSS J N-CLE K DNU L NC M NC N NC P NC NC NC NC NC NC NC NC NC DNU DNU N-IO8 DNU NC NC N-WE# N-WP# DNU R-CE# R-CRE VSS N-IO1 DNU N-IO2 N-ALE A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ18 VCCQ A/DQ1 A/DQ0 DNU N-IO3 N-VSS VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# N-VCC N-VSS VCCQ A16 A20 AVD# DNU F-RST# F-WP# A18 F-CE# VSSQ DNU N-PRE N-RE# F-RDY/ R-WAIT A21 VSS CLK VCC WE# F-ACC A19 A17 A22 N-IO4 DNU ORNAND Flash Only N-RDY DNU DNU R-LB# R-UB# N-IO5 DNU N-IO6 DNU pSRAM Only NC DNU DNU N-IO7 DNU NC NC NOR Flash 1 Only NC NC NC NC NC Do Not Use NC No Connect NC NOR Flash/pSRAM Shared Only 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Legend
Note: Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP S75NS128NBG S75NS128NBF
Flash-Only Addresses A22-A21 A22-A21
Shared Addresses A20-A16 A20-A16
Shared ADQ Pins ADQ15 - ADQ0 ADQ15 - ADQ0
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Data
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Information)
4.2.1
Lookahead Connection Diagram
Figure 4.1 112-ball x16 MUX NOR FLASH (Bus 1) + x16 MUX pSRAM (Bus 1) + x8/x16 ORNAND (Bus2)
1 A NC B NC C NC D NC E DNU F N1-CE# N-RE# F-RDY/ R-WAIT G N-VCC N-VCC H N-VSS J N-CLE K DNU L NC M NC N NC P NC NC NC NC NC NC NC NC NC DNU DNU N-IO0 N-IO8 NC NC N-WE# N-WP# A24 R-CE# R-CRE VSS N-IO1 N-IO9 N-IO2 N-ALE A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 N-IO18 N-IO3 NOR Flash Shared Only N-VSS VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# VCC VSS VCCQ A16 A20 AVD# A23 F-RST# F-WP# A18 F1-CE# VSSQ N-IO11 N-PRE A21 VSS CLK VCC WE# F-ACC A19 A17 A22 N-IO4 N-IO12 ORNAND Flash Only N-RDY N2-CE# F2-CE# R-LB# R-UB# N-IO5 N-IO13 N-IO6 N-IO14 pSRAM Only NC DNU DNU N-IO7 N-IO15 NC NC NOR Flash 1 Only NC NC NC NC NC Do Not Use NC No Connect NC NOR Flash/pSRAM Shared Only 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Legend
NOR Flash 2 Only
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Information)
4.3
Physical Dimensions
Figure 4.2 MMB112--11 x 13 mm, 112-ball VFBGA
PIN A1 CORNER
INDEX MARK
14 13 12 11 10 9 8 7 6 5 4 3 2 1
D
A
eD
D1
PIN A1 CORNER
A B C D E F G H J K L M N P
SE 7 E1
E eE
WVUTRPNML
K
J
HGFEDCBA
0.15 C (2X)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TOP VIEW
B
0.15 C (2X)
7
SD
0.20 C
BOTTOM VIEW
A A2 A1
6
SIDE VIEW b
M C AB MC
C
0.08 C
112X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.25 MMB 112 N/A 13.00 mm x 11.00 mm PACKAGE MIN --0.20 0.94 NOM ------13.00 BSC 11.00 BSC 8.50 BSC 6.50 BSC 18 14 112 0.30 0.50 BSC 0.50 BSC 0.25 BSC
1C~1M,2A,2B,2E~2K,3A,3B,3N,3P,4A,4B,4N, 4P,5A,5B, 5C,5M,5N,5P,6A~6D,6L~6P,7A~7E, 8A~8E,8K~8P,9A~9D,9L~9P,10A~10D, 10L~10P,11A~11E,11K~11P,12A~12E, 12K~12P,13A~13D,13L~13P,14A~14C, 14M~14P,15A,15B,15N,15P,16A,16B, 16N,16P,17A,17B,17N,17P,18C~18M
1. 2. 3. NOTE PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.35 BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 6 7 4. 5.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3558 \ 16-038.29 \ 4.27.6
MAX 1.40 --1.11
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Data
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Information)
5.
5.1
Revision History
Revision A (May 3, 2006)
Initial release.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.
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